THIS PAPER WILL DESCRIBE a 1Mb DRAM with a typical RE access time of 80ns. One mode of operation allows a 2Oblb/s data rate with relaxed system requirements*. A single 5V supply powers the devicywhich dissipates 160mW for a 260ns cycle. During standby (RE high), the dissipation is 0.5mW for TTL level inputs. The DRAM is packaged in an lbpin, 300-mil plastic DIP. A mask option allows the DIP pin out to meet either the proposed JEDEC standard or an evolutionary pattern which is more compatible with the standard 256K DRAM 16-pin package pin out.Circuit design, emphasizing reliability, provides limiting of maximum internal stress levels. The maximum voltage levels of boosted nodes are controlled;junctions are not operated near their breakdown voltages and transistors are not operated near punch through. This control is particularly important at high Vcc levels.from hot carrier effects is another well known reliability concern, and thus, both the device structure and the circuitry were designed to avoid hot-carrier problems. The N-channel device structure design put a premium on the reduction of the peak electric field in the channel. In addition, the circuit design avoided biasing of N-channel transistors in the high substrate current regime of operation.An on-chip substrate bias generator has been used to power the P-type substrate to a negative voltage level (Vbb). This serves to improve the isolation characteristics of parasitic transistors, reduce the possibility of minority carrier injection, and help prevent latch-up during operation. Also, the substrate bias allows the chip to tolerate input level undershoot. However, the Vbb generator has a relatively high output impedance, which could result in the substrate being susceptible to positive voltage excursions during chip power-up by capacitive coupling to Vcc. Such an excursion could initiate latch-up if not limited to a fraction of a diode forward voltage. The substrate voltage excursion is limited by the ballasting capacitance of the grounded memory cell field plate and by devices which clamp the substrate to Vss until the generator is active. The Vbb generator itself is designed to avoid minority carrier injection during operation.The susceptibility of the N-channel transistors to degradation __ *Fast Column(TM).A m t i m i n g mode, fast cohnn", has simplified board timing implications where data rates are up to 20MHz. This mode is similar to page mode, but the output (Q) is kept active between successive m r e a d cycles; Figure 2. Column addresses are strobed in at the falling edge of m, so that address skew does not affect access time. In the fast column mode, the rising edge of E d o e s not tri-state the output. Furthermze, a column cycle which has e n initiated by a falling edge of CE is allowed to finish even if CE rises again before the access is complete; in this case, internal timing is provided for the recovery of the column circuitry. Thus, most of the constraints on t h e m r i s i n g edge are removed, allowing a reduction in the signal bandwi...

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