A 1 nA current reference circuit is designed in semiconductor laboratory (SCL) 0.18 μm standard threshold voltage CMOS technology under 1.8 V power supply. The reference current is extremely immune to supply variation and shows a line sensitivity of 0.002%/V at post layout simulation level, over a wide range of supply variation from 0.5 V to 3.5 V. The line sensitivity is much smaller than any relevant data so far reported. In addition, it has a very low temperature coefficient of 214 ppm/°C over a temperature variation from −50°C to 50°C. The circuit consumes a total power of 588 nW. The reported results are also studied at various process corners and under variable process parameters like oxide thickness and threshold voltage of transistors. A satisfactory behaviour of the circuit is obtained in all cases. The accuracy of the simulation results is validated through quite close matching of the results with that obtained through rigorously developed theoretical models.

No abstract