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Generalized multiprotocol label switching (GMPLS) with wavelength division multiplexing (WDM) technology is a very promising protocol technology for future optical networks. GMPLS technology interconnects new and legacy networks by automating connection provisioning and traffic engineering. The present electrical interconnects for the system on chip (SoC) are unable to satisfy the multiple design requirements of bandwidth, data rate and latency. In this paper, for the first time we have proposed a micro resonator based GMPLS router for optical network on chip (ONoC). The evolution of such a router node on integrated circuit technology will cause the system design to move towards a communication-based architecture. The concept of an integrated GMPLS optical interconnect will be a potential technological solution, alleviating some of the more pressing issues involved in exchanging data between cores in SoC architectures. The investigation for ONoC was carried out at the physical level, where the system performance on the basis of crosstalk, blocking probability, offered traffic load and packet error rate (PER) was analyzed.

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