We generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices we label subgraphs which partition the given graph. We can achieve much better running times if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, our algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with a state-of-the-art routing tool on leading-edge industrial chips.

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In our paper we present new detailed routing algorithms dealing with challenges in advanced technology nodes, such as complex design rules and multiple patterning. We combine our routing tool, BonnRoute, with an industrial router for cleaning up remaining design rule violations and demonstrate superior routing results over that industrial router on real-world multiple patterning designs. This paper has never been submitted for publication anywhere else.On behalf of all authors, Michael GesterAbstract-We present algorithms for routing in advanced technology nodes, used by BonnRoute to obtain efficient and almost design rule clean wire packings and pin access solutions. Designs with dense standard cell libraries in presence of complex industrial design rules, with a special focus on multiple patterning lithography, are considered. The key components of this approach are a multi-label interval-based shortest path algorithm for long on-track connections, and a dynamic program for computing packings of pin access paths and short connections between closely spaced pins. The multi-label path search implementation is very general and is driven with different labeling rules, allowing to trade off runtime against accuracy in terms of obeyed design rules. We combine BonnRoute with an industrial router for cleaning up the remaining design rule violations, and demonstrate superior results over that industrial router in our experiments in terms of wire length, number of vias, design rule violations and runtime.