Although the conventional methods for strong attachment of chitosan onto stainless steel require many steps in different solvents, it has been demonstrated in this work that covalent grafting of chitosan on a steel surface can be easily achieved through the formation of a self-adhesive surface based on aryldiazonium seed layers. Initially, a polyaminophenyl layer is grafted on a stainless steel surface by means of the one-step GraftFast(TM) process (diazonium induced anchoring process). The grafted aminophenyl groups are then converted to an aryldiazonium seed layer by simply dipping the substrate in a sodium nitrite acidic solution. That diazonium-rich grafted layer can be used as a self-adhesive surface for subsequent spontaneous coating of chitosan onto the steel surface. X-ray photoelectron and impedance electrochemical spectroscopies were used to characterize the pristine and modified steel samples. As evidenced from impedance and linear polarization results, the primary polyaminophenyl layer characterized by a high charge transfer resistance contributed to better protection against corrosion of the resulting chitosan-coated steel in sulfuric acid medium.

Via-Last metallization of High Aspect Ratio Through Silicon Via (HAR TSV) for 3D integration is challenging. Indeed, the formation of a uniform and conformal dielectric to insulate HAR TSVs in Via-Last process flow is difficult to achieve for any physical deposition process. In this study, we present the first reported HAR copper TSVs, insulated by highly conformal electrografted poly-4-vinylpyridine (P4VP) in Via-Last process-flow. As a demonstration, this allowed the metallization of HAR copper TSVs for die-to-die 3D integration of a 22 × 22 photodiode array tier onto a CMOS control electronics ASIC.

Through-Silicon-Vias (TSV) are the key to 3D integrated microsystems. Their fabrication leads to reliability issues linked to the thermo-mechanical stress induced in the silicon around the vias. In this work, we propose to reduce the silicon residual stress in high aspect ratio copper TSVs (HAR TSV) using an electrografted polymer insulator, poly-4-vinylpyridine (P4VP), in replacement of the traditional silicon oxide layer. We use Raman spectroscopy to make the first investigation of the residual stress in the Si around P4VP insulated TSVs and compare it to SiO2 insulated TSVs. The results show that P4VP acts as a stress buffer layer because of its particular mechanical properties as the measured residual stress in Si is significantly reduced at room temperature around the polymer insulated HAR TSVs. The potential benefits of such a technology are not only a better thermo-mechanical reliability of 3D integrated microsystem, but also a greater integration density.

Alchimer develops alternative wet solutions based on electrografting (eG™) and chemical grafting (cG™) proprietary technologies. eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces, and enables self-oriented growth of thin coatings of various materials, especially polymer and metals, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Due to outstanding thermal, mechanical and electrical properties, electrografted polymer layers are an efficient insulation layer for TSV applications. In this paper, we fill focus on the copper diffusion barrier properties of this eG polymer layer and the associated Cost of Ownership (CoO) reduction for TSV metallization.