We characterized the effects of surface morphology on the electrical properties of n‐GaN drift‐layers by using scanning internal photoemission microscopy (SIPM). We grew 12‐μm‐thick low carrier concentration (approximately 1 × 1016 cm−3) n‐GaN layers with both flat and wavy surface morphologies on freestanding GaN substrates by metal organic chemical vapor deposition. In the SIPM results, the samples with flat surfaces exhibited a uniform photocurrent distribution independently of the carrier concentration. In contrast, wavy patterns in the photocurrent maps were the same as the surface morphology for samples with low carrier concentration. These results indicate that the amount of C incorporated during the growth was affected by the off‐angle of the GaN surface, and the carrier compensation by C atoms was changed. We demonstrated that SIPM is a powerful tool for nondestructively visualizing the inhomogeneity of the carrier compensation over the wafers.

GaN MOS C-V device simulations considering various types of interface and bulk traps are performed by transient-mode. The simulations explain various features of C-V curves, such as plateau, hysteresis, frequency dispersions which are arising from the complicated combinations of interface and bulk deep level traps. The present method is a good theoretical tool to understand the physics behind various un-ideal C-V measured curves.

SiNx films formed on n-SiC layers have been characterized by using scanning internal photoemission microscopy (SIPM) in a metal–insulator–semiconductor diode structure. After applying forward-biased voltage stress up to 30 V, the diode was partially degraded. SIPM clearly imaged the degradation pattern with a large photocurrent, which was consistent with the microscopy image. These results clarified that the partial degradation induced a leak path with a low energy barrier.

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