A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16 x 16 FFT when the first bit-serial blockparallel data is obtained. The image sensor produces a 16 x 16 range image from a pair of 256 x 256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance. IntrodnetionThere are more and more increasing demands in the industry for real-time range sensing 6om simultaneously captured multiple images. The range image sensor to inspect proper placements of the small components on printed circuit boards (PCB's) is an example. Triangulation-based light stripe method widely used in robot vision [ l ] is not always suitable for range imaging of millimeter-size objects, and needs a complicated mechanical scanning system.For high-speed image processing, the bottleneck of interface between image sensors and signal processing system is .one of the most serious problems. In this paper, a binocular CMOS range image sensor based on bit-serial block-parallel (BSBP) interface architecture solving this problem is presented. The proposed CMOS sensor with the BSBP output using a cyclic pipelined AID converter (ADC) array provides the maximum performance for calculating Fourier transform required to execute the stereoscopic range imaging. This architecture using cyclic pipelined ADC's allows us to obtain the range image resolution of 16 x 16 pixels at 300 framesis together with an external processor. Fig. 1. Range imaging system 270 0-7803-7310-3/02/$17.00Q2002 IEEE Range Imaging SystemThe range imaging system is shown in Fig. 1. Each 256 x 256 pixel array is divided to 16 x 16 pixel blocks with 16 x 16 pixels, Using corresponding block pairs, parallax values are estimated by the phase only correlation (POC) algorithm and the range image of 16 x 16 pixel resolution is obtained. The POC is defined as a modified correlation such that the amplitude spectrum is replaced by a constant in the process of calculating correlation using Fourier transform [2]. A couple of lenses is placed on top of the two image sensors in such a way that the optical axes cross at the center of datum plane in order to make the parallax to be zero on the plane. Implementation Fig. 2 shows the block diagram of the binocular CMOS image sensor for the range imaging system. An important requirement for the stereoscopic range imaging is the exact placement of two image sensors. The parallel placement of two sensors without any rotation of focal plane is particularly important. The binocular CMOS image sensor developed is essential for this purpose because the two sensors can be placed with photolithographic accuracy of LSI technology.

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations.