In most data-centric embedded systems, optimum implementation of a few key applications is required to realize a high costperformance system. However, each application requires operations of a different type and a different performance range. Therefore, a configurable media processor is a suitable solution for such embedded systems. This 4GOPS 3way-VLIW imagerecognition processor for an automobile system is based on a configurable media processor.The configurable media-processor is characterized by template architecture, common components and custom components. The common components are used for every application and their configuration can be optimized for a target application. The template architecture defines internal bus structure and extension interfaces for custom components. The custom components are designed for each target application. All components are assembled together along the template architecture at design-time and implemented by standard-cell design. Figure 9.5.1 shows the template architecture of the configurable media-processor. It consists of a processor core, on-chip memory, user-defined instruction units, a coprocessor, hardware (HW) engines and a DMA controller (DMAC). The processor core and on-chip memory are categorized as common components. The others are the custom components. The processor core has RISC-like architecture with a 5-stage pipeline. It has optional instructions. Extension interfaces necessary for custom components can be implemented.One of the most important features of the media-processor is a VLIW extension. The processor core has VLIW processing mode to support a VLIW coprocessor tightly coupled at pipeline level. In the VLIW processing mode, a fixed-length VLIW instruction is fetched every cycle. The upper portion of an instruction is executed by the processor core and the lower portion is executed simultaneously by the coprocessor. A mode-change between the VLIW processing mode and the normal processing mode is by instructions for subroutine call and return. While the processor core is responsible for instruction execution flow and memory access, the coprocessor executes application-specific operations. By substituting a co-processor customized for each application, application-specific VLIW processors are obtained.The image processor is designed for an automatic automobile rear and side surveillance system. The system detects passing vehicles by processing image data from a rear-view camera to support safe driving [1]. Figure 9.5.2 shows a block diagram of the image processor. The chip integrates parallel I/O (PIO), ROM controller (ROMC), capture unit, andSDRAM controller (SDRAMC). The image processor is controlled by a micro controller through the PIO.The ROM controller supports 4MB E 2 PROM. Image data are taken from the capture unit. The SDRAM controller provides a glueless connection to a 125MHz 8MB(32bx512kwordx4Bank) SDRAM. The I/O pins of the SDRAM interface are located on both edges of the chip so an SDRAM can be mounted on the reverse face of a print circui...

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm 2 die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

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