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High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spintransfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T + 1FeFET and 2T + 1FeFET designs proposed in early works, as well as SRAM, STT-RAM, and RRAM. Our evaluation of a 64×64 FeFET-RAM array shows that the area, READ delay, and static power are reduced by ∼5.3×, ∼1.5×, and ∼74×, respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows ∼50× improvements in terms of WRITE energy with respect to STT-RAM and RRAM counterparts. INDEX TERMS Emerging technologies, FeFETs, memory. I. INTRODUCTION In state-of-the-art processors, cache structures are typically comprised of complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. While transistor scaling has helped to reduce memory cost and improve cache capacity, low density and high leakage power associated with MOSFET SRAMs make it challenging to satisfy the growing memory demands from data intensive programs via 2-D CMOS-based SRAMs. The aforementioned challenges with SRAM have led to the search for alternative on-chip memory structures. Nonvolatile memories based on emerging technologies such as spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and phase-change memory (PCM) have

Due to their CMOS compatibility, hafnium oxide based ferroelectric field-effect transistors (FeFET) gained remarkable attention recently, not only in the context of nonvolatile memory applications but also for being an auspicious candidate for novel combined memory and logic applications. In addition to bringing nonvolatility into existing logic circuits (Memory-in-Logic), FeFETs promise to guide the way to compact Logic-in-Memory solutions, where logic computations are examined in memory arrays or array-like structures. To increase the area-efficiency of such circuits, a dense integration of FeFETs and standard FETs is essential. In this paper, we show that the ultra-dense cointegration of FeFETs and nFETs (28nm HKMG) with shared active area does not alter the FeFET's switching behavior, nor does it affect the baseline CMOS. Based on this, we propose the integration of a FeFET-based, 2-input look-up table (memory) directly into a 4-to-1 multiplexer (logic), which is utilized directly in a 2TNOR memory array or stand-alone circuit. The latter one dramatically reduces the transistor count by at least 33% compared to similar FeFET-based circuits. By storing values of the look-up table in a nonvolatile manner, no energy is consumed during standby mode, which enables normally-off computing. To take another step towards novel Logic-in-Memory designs, we experimentally demonstrate a very compact in-array 2T half adder and simulate an array-like 14T full adder, which exploit the advantages of the array arrangement: easy write procedure and a very compact, robust design. The proposed circuits exhibit energy-efficiency in the (sub)fJ-range and operation speeds of 1GHz.INDEX TERMS Adder, ferroelectric FET (FeFET), hafnium oxide (HfO 2 ), logic-in-memory (LiM), look-up table (LUT), memory array, multiplexer (MUX), ultra-dense integration.

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