A Multiplier is an essential component that dictates the performance of modern computing systems. However, high power dissipation of CMOS multiplier circuits has become a major concern in sub 45 nm technology nodes. Recently, emerging non-volatile memory (NVM) based hybrid circuits have gained a lot of attention due to the prominent feature of negligible static power consumption. Magnetic tunnel junction (MTJ) based spin-torque memories have been used for low power applications. However, spin-transfer torque magnetic random access memory (STT-MRAM) based hybrid CMOS/MTJ circuits exhibit higher write energy and longer incubation delay. In this work, a differential spin Hall (DSH)-MRAM cell is employed for logic and circuit applications. It stores a pair of complementary bits with low write voltage and reduced area. The variability analysis of DSH-MRAM signifies the availability of sufficient margin between different resistance states. Different types of 8x8 and 4x4 hybrid CMOS/MTJ multipliers are analyzed using DSH based adders and logic gates. The proposed multipliers consume approximately 20% less power and exhibit 19% improvement in power-delay product (PDP) characteristics compared to CMOS based multipliers.