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Abstract-With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Event-transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of Single-Event-Upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure and gate delays on Single-Event-Upset sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian Network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.

We propose a novel formalism, based on probabilistic Bayesian networks, to capture, analyze, and model dynamic errors at nano logic for probabilistic reliability analysis. It will be important for circuit designers to be able to compare and rank designs based on the expected output error, which is a measure of reliability. We propose an error model to estimate this expected output error probability, given the probability of these errors in each device. We estimate the overall output error probability by comparing the outputs of an ideal logic model with a dynamic errorencoded model. We use of Bayesian inference schemes for propagation of probabilities. Since exact inference is worst case NP-hard, we use two approximate inference schemes based on importance sampling, namely EPIS(Evidence Prepropagated Importance Sampling) and PLS (Probabilistic Logic Sampling), for handling mid-size benchmarks having up to 3500 gates. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results.