Cloud computing is a model for enabling convenient, ondemand network access to a shared pool of configurable computing resources that can be rapidly provisioned and unconfined with minimal management effort. Our work mainly targets the learning community by providing an efficient cloud compiler as SaaS by coalescing the two major concepts called cloud computing and open source which helps to diminish the troubles of portability, compatibility, power and storage space by making use of the concept of cloud compiler. The basic underlying architecture to deploy a cloud compiler is the establishment of private cloud under linux environment, which provides hosted services to a limited number of people and the service is distributed in the heterogeneous manner. Private cloud makes the cloud infrastructure based on Ubuntu Enterprise Cloud (UEC) scalable as per the requirement. And our cloud compiler allows a programmer to pick up the fastest or the most convenient tool to compile the code and remove the errors. The validity of our approach is then verified with the experimental results. Also we have made a performance analysis and the experimental results shows that the performance of cloud compiler is more efficient compared to all other normal compiler. Hence our proposed cloud compiler is considered to be the best performers among the various compilers.

The power consumption of circuit design finds how much energy is consumed per operation. The large portion of the power consumption in integrated circuit is mostly depends on storage element and clock signal distribution. A clock is used to ensure that all operation occur at the same instant. The important technique for efficiency is the use of double edge triggered flip fops (DETFF S ). Which can be maintaining the same throughput of single edge triggered flip fops while using the half of the clock frequency. Clock gating is another good technique to reduce the dynamic power consumption. However incorporating the clock gating technique with double edge triggered flip fops further reduce the dynamic power consumption which creates the asynchronous sampling. It can be avoided by changing the D flip flop master latch circuit parameter.