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In low power SoC for portable applications 0.5V operation will be required around '2010 to keep the total chip power fixed to 100mW with scaling [1]. Suppression of transistor static leakage current to 100pA/µm is also required to keep the static power level below 10% of the total power. One of the significant issues for these requirements is the severe degradation of the operation speed. Another key issue is the great influence of voltage fluctuation on the operation speed. To solve these issues, Bulk Dynamic threshold MOSFETs (B-DTMOS) and a Self-Adaptive Power supply System (SAPS) are investigated. Figure 22.9.1 shows the schematic cross section and the Ids-Vgs characteristics of the B-DTMOS compared to conventional MOS (Conv.MOS) with substrate voltages of 0V and 0.5V. The use of a Low Capacitance Sidewall Elevated Drain (LCSED) structure enabled a 60% reduction in both the occupation area of the serially connected transistor and the junction capacitance [3]. The main features of B-DTMOS characteristics are that the drive current is more than three times greater than Conv.MOS at 0V and that the leakage current is about two orders of magnitude smaller than Conv.MOS at 0.5V. A problem of high static leakage current due to the parasitic vertical bipolar transistor was suppressed by limiting the supply voltage to 0.5V.A gate array (GA) cell library containing 55 GA cells using B-DTMOS for the design of LSIs using 0.25µm design rules is developed. A Fully Static True Single Phase Clock (FS-TSPC) F/F circuit is designed and shown in Fig.22.9.2. The power dissipation of the four-stage toggle counter using 0.5V B-DTMOS with FS-TSPC F/Fs is decreased to 1/28 of that of the Conv.MOS operating at 2.5V. A CDMA MF LSI containing 130k gates is designed with a top down design methodology using the cell library. The cell area normalized to a standard CMOS cell area is also shown in Fig.22.9.2. Using the local interconnect ability of the LCSED structure to the fullest, a cell area almost equal to, or in some cases smaller than, that of the standard CMOS is achieved. Figure 22.9.3 shows speculated trend of B-DTMOS on chip clock frequency compared to that of High Performance (HP) logic [1]and Low Operation Power (LOP) Conv.MOS with 100pA/µm leakage current. Speculation is done by device simulation. The predicted speed of B-DTMOS is about 1/10 of that of HP throughout the generations. In the year 2010 almost same speed and about 1/2 the power dissipation will be realized by B-DTMOS compared to that of the Conv.MOS. After 2013 both speed and power dissipation of B-DTMOS will be superior to that of the Conv.MOS. Figure 22.9.4 shows the measured dependence of "Best case", "Typical" and "Worst case" inverter delay time on power supply voltage for the Conv.MOS, B-DTMOS and B-DTMOS with adaptive voltage control. 50mV variation of threshold voltage and supply voltage and from -40 to 85 O C temperature range were assumed. For the Conv.MOS the ratio of the "Best case" to the "Worst case" delay was about 50. It is, therefore, almost impos...

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