Abstract. In this article we consider a design of a multiplier for the multiplication of complex numbers. The complex numbers are packed into one 32-bit word. They are represented by two 13-bit parts with the same 6-bit exponent. Multiplication of complex numbers is examined from the perspectives of performance, complexity and silicon area. The design is unique and combines shared Booth encoding for the real and imaginary parts including only one combined modified Wallace tree of 4:2 adders for each part. The regular Wallace tree is compared with the tree of 4:2 adders. This design results in a more compact wiring structure and balanced delays resulting in a faster multiplier circuit. The number of adders used in the multiplier is also reduced. We consider VLSI CMOS technology and the relevant characteristics as they impact the implementation and performance.

An architecture for ASIC macro-cell implementing a complex number multiplier with applications in a digital signal processing ASIC chip is described. The complex numbers are packed into one 32-bit word. The design is unique and combines shared Booth encoding for fhe real and imaginary parts including only one combined modified Wallace tree. We compared the regular Wallace tree and the tree of 4:2 adders for the complex multiplier implementation. We took advantage of 4:2 adders in implementing the combined bit compression tree for each part. This design resulted in a more compact wiring structure and balanced delays resulting in faster multiplier circuit. The number of adders was also decreared.

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