Table 1 Comparison of potential sub-10 nm III-V device architectures Fig. 1 and 2 Schematic of ET-QW InAs MOSFETs and TEM images for L g = 50 nm ET-QW InAs MOSFETs with T QW = 5 nm. Note that 3-nm Al 2 O 3 was used as a gate insulator, together with MBE-grown 2-nm InP, leading to EOT = 2 nm. This paper reports Extremely-Thin-Body (ETB) InAs quantum-well (QW) MOSFETs with improved electrostatics down to L g = 50 nm (S =103 mV/dec, DIBL = 73 mV/V). These excellent metrics are achieved by using extremely thin body (1/3/1 nm InGaAs/InAs/InGaAs) quantum well structure with optimized layer design and a high mobility InAs channel.The ETB channel does not significantly degrade transport properties as evidenced by g m >1.5 mS/μm and v inj = 2.4 10 7 cm/s. Abstract:Introduction: The superior electron transport properties of III-V materials enable an attractive route to V dd scaling at sub 10 nm nodes. Extremely thin (ET) architectures (finFET or planar ETB) are a choice of technology at these geometries to maintain electrostatic integrity and control short channel effects (SCE) [1-3]. However, thinning down a channel degrades carrier transport properties. For the first time, we report ETB-QW L g = 50 nm InAs MOSFETs that exhibits excellent SCE control and favorably benchmarks an injection velocity (v inj ) against other III-V and Si devices. This comparison demonstrates that channel thickness can be scaled to at least 5 nm and the v inj advantage over Si maintained, demonstrating a potential scaling pathway to sub 10-nm technology node.Experimental: Table 1 as a motivation of this work compares different device architectures that can be considered for aggressively scaled III-V devices for future logic applications. The electrostatic control provided by ET-QW single gate devices may not be sufficient for sub-10nm nodes, but this architecture provides an excellent test structure to investigate the potential electron transport of multi-gate device with similar body/fin/nanowire width. Figs. 1 sand 2 show a cross-section of the device structure and corresponding TEM images of an L g = 50 nm device. MBE-grown 2-nm InP insulator was used to reduce access resistance and improve charge control, EOT and immunity to short channel effects as well as to improve D it [3].Extremely-Thin-Body of In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As (1/3/1nm) composite channel with inverted Si δ-doping and 5 nm In 0.52 Al 0.48 As spacer was chosen to improve carrier transport, electron confinement in the channel and electrostatic integrity. In a calibration structure, the Hall mobility was 8,400 cm 2 /V-s with n s,ch = 9.4 x 10 11 /cm 2 at 300 K. This is only about 24 % lower than the value obtained in a 10 nm thick In 0.7 Ga 0.3 As HEMT heterostructure [4], revealing that the use of 3-nm thin InAs sub-channel was effective in mitigating a degradation of carrier transport property.In 1D self-consistent Schrodinger-Poisson calculation for T QW = 5 nm epi structure, as the channel is thinned down, the carrier concentration in the channel at the acces...

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<10nm, ND=5x10 19 cm -3 , ρc= 6Ω.μm 2 and Dit = 4x10 12 eV -1 cm -2 . Si VLSI fab and ESH protocols have been developed to enable advanced process flows.