Present address: Arizona State University, School of Electrical, Computer and Energy Engineering, 551 E. Tyler Mall, Tempe, AZ 85287, USA.Reducing wafer thickness while increasing power conversion efficiency is the most effective way to reduce cost per Watt of a silicon photovoltaic module. Within the European project 20 percent efficiency on less than 100-mm-thick, industrially feasible crystalline silicon solar cells ("20plms"), we study the whole process chain for thin wafers, from wafering to module integration and life-cycle analysis. We investigate three different solar cell fabrication routes, categorized according to the temperature of the junction formation process and the wafer doping type: p-type silicon high temperature, n-type silicon high temperature and n-type silicon low temperature. For each route, an efficiency of 19.5% or greater is achieved on wafers less than 100 mm thick, with a maximum efficiency of 21.1% on an 80-mm-thick wafer. The n-type high temperature route is then transferred to a pilot production line, and a median solar cell efficiency of 20.0% is demonstrated on 100-mm-thick wafers.

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