This paper proposes a design procedure of the LCL filter for energy storage system (ESS). The main goal is satisfied filter performance and simple calculation for highpower ESS. Filter design is derived from transfer function by inverter, inductor and capacitor. The proper value of inductor is used a filter design, ESS is applied in the experimental setup (1.5MW Class). Simulation investigation and experimental results are presented to verify the theoretical design procedure and to demonstrate to system performance.

In this paper, interface circuits that are suitable for point‐to‐point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi‐gigabits per‐second between two chips with a point‐to‐point interconnection, the input receiver uses an on‐chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode‐connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 µm dual gate oxide CMOS technology.