Abstract-This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold sourcecoupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice.

Abstract-The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better powerdelay performance compared to their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to lower sensitivity to the process and supply voltage variations make STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed.