Metallic vanadium was successfully produced starting from vanadium sul de by applying electrolysis in molten CaCl 2 . Vanadium sul de lled in a cathodic Ti basket and a graphite anode were immersed in the melt of CaCl 2 -CaS at 1173 K in Ar, and the electrolysis was conducted at a cell voltage of 3.0 V. Sul de electrolysis did not form carbon deposit and was free from carbon contamination, while carbon powder was formed on the cathode in the oxide electrolysis using the melt of CaCl 2 -CaO. When the CaS content in the molten CaCl 2 increased, electrolysis current increased resulting in fast smelting while the oxygen and sulfur contents in metallic vanadium increased. Oxygen and sulfur contents as low as 3390 ppm and 210 ppm, respectively, were achieved by supplying about four times more electrical charge than stoichiometry.

In order to check the solubility of CaS during sulfide reduction in molten CaCl 2 , the mixture of CaCl 2 and a small amount of CaS was melted in Ar at the range from 1123 K to 1223 K. The melt was sampled by quartz tube and rapidly solidified. The solidified samples showed a lamella structure with CaS particles, which results in a simple eutectic reaction between CaCl 2 and CaS. Using ICP-AES analysis, the saturation of CaS was found to be completed within 1.8 ks, and 1.77 « 0.1 mol%CaS at 1173 K was measured as the solubility limit at the initial composition of 3.0 mol%CaS. A tentative phase diagram of CaCl 2 CaS binary system was proposed based on the solubility analysis in these temperatures and eutectic structure.

Solubility of CaS in molten CaCl 2 65 mol%LiCl eutectic salt was examined by sampling of CaS saturated salt and ICP analysis. The handling in dried environment and an adequate mass of melt were applied for reliable measurements, in addition to suppression of inclusion of CaS particles. The solubility limit was found to be 0.22 « 0.05, and 0.31 « 0.05 mol%CaS at 873 K and 973 K, respectively. This saturation value was less than 1.77 « 0.1 mol%CaS in pure CaCl 2 at 1173 K. [

This study reposts the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) by the transfer printing of a gate dielectric in conjunction with a poly(vinyl-alcohol) (PVA) coating for carrier doping. The spin-coated PVA film increases the carrier concentration in MoS2, while the back-gate MoS2 FET cannot be turned off. The transferred top-gate structure with the PVA coating makes it possible to turn off the fabricated device without permanent damage to MoS2. The results of this study suggest interesting directions for the research and development of two-dimensional material-based functional devices.

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs. For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively. Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts. Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V. Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits. References [1] Q. H. Wang, K. K. Zadeh, A. Kis, J. N. Coleman, and M. S. Strano, Nat. Nanotechnol. 7, 699 (2012). [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, 1998). [3] L. Yu, A. Zubair, E. J. G. Santos, X. Zhang, Y. Lin, Y. Zhang, and T. Palacios, Nano Lett. 15, 4928 (2015). [4] C.-S. Pang and Z. Chen, 2018 76th Device Research Conf. (DRC), p. 1, 2018. [5] M. Tosun, S. Chuang, H. Fang, A. B. Sachid, M. Hettick, Y. Lin, Y. Zeng, and A. Javey, ACS Nano 8, 4948 (2014). [6] T. Kawanago, T. Matsuzaki, R. Kajikawa, I. Muneta, T. Hoshii, K. Kakushima, K. Tsutsui, and H. Wakabayashi, Jpn. J. Appl. Phys. 61, SC1004 (2022). Figure 1