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To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

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