Unfortunately, many persons are injured or killed during disasters. The problems of paper triage tags, which are widely used at disaster scenes, include an inability to show the current priorities of casualties and a failure to collect the physiological conditions of the casualties. To save lives, this paper proposes an electronic triage system that consists of two types of electronic triage tags and an electronic triage server. The electronic triage tag continuously monitors the vital signs of casualties and transmits them to the electronic triage server, and the electronic triage system shows the current priorities of the casualties. Experimental results show that our proposed electronic triage system can save more lives than paper triage tags.

SUMMARYThis paper studies the static mapping of multiple applications on embedded many-core SoCs. The mapping techniques proposed in this paper take into account both inter-application and intra-application parallelism in order to fully utilize the potential parallelism of the manycore architecture. Two approaches are proposed for static mapping: one approach is based on integer linear programming and the other is based on a greedy algorithm. Experiments show the effectiveness of the proposed techniques.

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Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core System-on-a-Chip (SoC) since it offers better scalability than traditional bus-based interconnection. In this work, we have developed a fast simulator of NoC architectures using QEMU and SystemC. QEMU is an open-source CPU emulator which is widely used in many simulation platforms such as Android Emulator. In the proposed simulator, each CPU core is emulated by a QEMU, and the network part including NoC routers is modeled with SystemC. The SystemC simulator and QEMUs are connected by TCP sockets on a host computer. Our simulator is fast because QEMUs run in parallel on a multi-core host computer or even multiple host computers. Also, our simulator is highly retargetable because QEMU provides a variety of CPU models and we use QEMU as is. In our experiments, our simulator successfully simulates a 108-core NoC in a practical time. We have also confirmed the scalability and retargetability of our NoC simulator.