An on-chip noise monitor using a dual-mode analog to digital converter (ADC) is developed to detect the insertion of off-chip components as malicious attempts of power noise measurement attacks. A two-step sampling scheme selecting either synchronous or asynchronous clocking enables both real-time monitoring and high-resolution diagnosis of power supply noise, respectively. The monitor detects the change in power-line impedance and assumes the happening of physical contacts by an attacker’s device. A wide-band ADC with the bandwidth of 1 GHz facilitates the analysis of on-chip captured waveforms and the recognition of potentially inserted devices. Fabricated in 65 nm CMOS, the on-chip noise monitor is examined for the detectability of series resistors as well as parallel capacitors that are intentionally inserted on power lines. The experiments demonstrated the detection of a power current sensor in series to power lines, and also the attachment of an oscilloscope probe, through the analysis of on-chip captured power noise waveforms.

No abstract

No abstract

This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200 mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5 kΩ contact resistor on the backside of a 350 µm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40 µm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

No abstract