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A simulation model for the low-pressure chemical vapor deposition of polycrystalline silicon using a silane-hydrogen mixture in a multiwafer batch record has been developed. This model was employed to study the effects of temperature, flow parameters, reactor geometry, and wafer size upon the process, particularly the uniformity of silicon deposition. Potential improvements in the system performance were determined by utilizing optimum temperature staging and reactant injection schemes. The results also showed that nonuniform wafer spacing can improve deposition uniformity and wafer throughput while decreasing the process sensitivity to reactant flow rate variations.The manufacture of microelectronic devices involves the sequencing of processes involving thin film deposition, patterning, and doping. The formation of the film is performed by a variety of techniques including physical and/or chemical processes (Jensen, 1987). One of the most versatile of these methods is chemical vapor deposition (CVD). This process involves reacting flowing gases on a substrate to form the desired film. Energy for the reaction is provided by heat or by a plasma. CVD requires the diffusion of gaseous reactants to the hot substrate and adsorption, reaction, desorption, and diffusion of gaseous products back into the bulk gas, yielding a film on the substrate.

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