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We address the formal veri cation of the control so ware of critical systems, i.e., ensuring the absence of design errors in a system with respect to requirements. Control systems are usually based on industrial controllers, also known as Programmable Logic Controllers (PLCs). A speci c feature of a PLC is a scan cycle: 1) the inputs are read, 2) the PLC states change, and 3) the outputs are wri en. erefore, in order to formally verify PLC, e.g., by model checking, it is necessary to describe the transition system taking into account this speci city and reason both in terms of state transitions within a cycle and in terms of larger state transitions according to the scan-cyclic semantics. We propose a formal PLC model as a hyperprocess transition system and temporal cycle-LTL logic based on LTL logic for formulating PLC property. A feature of the cycle-LTL logic is the possibility of viewing the scan cycle in two ways: as the e ect of the environment (in particular, the control object) on the control system and as the e ect of the control system on the environment. For both cases we introduce modi ed LTL temporal operators. We also de ne special modi ed LTL temporal operators to specify inside properties of scan cycles. We describe the translation of formulas of cycle-LTL into formulas of LTL, and prove its correctness. is implies the possibility of model checking requirements expressed in logic cycle-LTL, by using well-known model checking tools with LTL as speci cation logic, e.g., Spin. We give the illustrative examples of requirements expressed in the cycle-LTL logic.