A crystalline oxide semiconductor (OS) FPGA capable of subthreshold operation is developed.To achieve subthreshold operation, the OS FPGA employs overdriving of a programmable routing switch and a programmable power switch for power gating by using OS FFT as an ideal floating gate with excellent charge retention. In a prototype chip fabricated with a 0.8-m OS/0.18-m CMOS hybrid process, while maintaining features realizing low power consumption proposed in our previous studies [1, 2], the following are shown: a configured combinational circuit operates at a minimum operating voltage (V min ) of 180 mV, a configured sequential circuit operates at V min of 190 mV with 12.5 kHz, and the minimum power-delay product scores 3.40 pJ/operation at 330 mV.

Transistor aging occurs in nanoscale LSIs and is a factor that degrades large scale integration (LSI) performance. Because aging decreases the switching speed of transistors, LSIs ultimately malfunction due to the increase in the propagation delay. This paper proposes a procedure starting from the estimation of the aging amount at the metal‐oxide‐semiconductor field‐effect transistor (MOS FET) level to that at the gate level. The aging effect at the MOS FET level is extracted from changes in the periods of two special ring oscillators. The aging amount at the MOS FET is estimated by using a calculation model based on an RC circuit. The estimated aging amount is used to estimate the increase in propagation delay due to aging at the gate level. Results of circuit simulations showed that the proposed procedure produced estimations with an error rate of less than 4.6% for the increase in switching delay, and less than 0.6% for the increase in threshold voltage. For estimation of path delay, the range of the error rate was from –22.7 to +11.4%. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

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