No abstract

some embedded designers desire optimize encryption processing especially for low-cost wireless communications that may be carrying or transmitting sensitive information. They can achieve energy and performance benefits by using dedicated hardware accelerators. However, implementing custom hardware accelerators require hand written register transfer level (RTL) development and debugging and are too time consuming for today's complex system-on-chip. Consequently, High Level Synthesis (HLS) brings a solution to decrease the design time of hardware and raise the level of abstraction beyond RTL flow. With CatapultC synthesis tool of Mentor Graphics, a designer can start from an embedded application running on a processor and then migrate parts of the program to hardware accelerators. In this work we offer a new Hardware/Software design flow using High level synthesis. We demonstrate the efficacy of this approach on the practical design example of a cryptographic module. The hardware accelerator is an AES-128 cryptographic module. The gain reaches 11.76% for encryption operation and 12.4% for decryption operation compared to the pure software implementation. This module is downloaded on Altera FPGA using the soft NIOSII processor to exchange data with the AES-128 accelerator.