Abstract. Transport Triggered Architecture (TTA) offers a cost-effective tradeoff between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complexvalued fast Fourier transform (FFT). The proposed processor consumes only 1.55 µJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.

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