No abstract

The on-device and target-less overlay (OVL) measurement adds various challenges to the conventional target-based one.1 Most of the common solutions are based on the use of high voltage SEM to have a high resolution and see-through capabilities to see both layers entirely. To ensure repeatability and robustness the measurement is also generally realized on dedicated targets.2–4 Another approach is explored in this work : it consists of a direct measurement on the device itself, without any dedicated target and using a CD-SEM that do not have see-through capabilities. To avoid any damage on the final device and to ensure a partial vision of the bottom layer, the measurement is realized post etch. What can a true on-device, target-less, SEM overlay metrology reveal of the process? To answer this question, a custom design-based on-device CD-SEM overlay metrology was developed.5 It allows measuring the overlay on any bilayer 2D structure, even partially hidden, provided that sufficient edges are visible. Thanks to this post-processing capacity to measure on partially hidden patterns, the CD-SEMs from the current tool park can be used and non-transparent layers can be investigated. After demonstrating the capability of the previously mentioned solution on synthetic SEM images,6 by taking advantage of the versatility of the method and of an improved bilayer contour extraction algorithm, one product wafer was measured densely at different steps of the process on several patterns. These extensive measurements aim to reveal overlay signatures at different spatial frequencies: intra-field, intra-chip and even inside a random logic array. This paper details and interprets the observed overlay measurement with models while investigating the matching between the different measurement patterns and the mismatches with the optical overlay. To conclude, the contour-based metrology offers the capability to extract highly valuable information from CD-SEM images and represents a great opportunity for on-device overlay measurement. By measuring directly the products’ patterns, the developed metrology shows a mismatch between optical and SEM measurements up to a couple of nanometers. A hybrid model, mixing SEM and optical measurements reduced by 15% the on-product residuals. Additionally, the local overlay variability could be evaluated and low amplitude chip signatures have been observed. This new information will help process engineers to improve the process characterization, leading to a better process control that results in an improved reliability.

The shift of semiconductor industry applications into demanding markets as spatial and automotive led to high quality requirements to guaranty good performances and reliability in harsh environments. As reliability is directly related to a well controlled process, characterizing the local overlay and its variations inside the chip itself becomes a real asset. While most available in-chip overlay metrologies require dedicated target or dedicated tools, we developed a new method that aims to augment the current SEM tool park into measuring the local overlay directly on the product. In a previous proceeding, this on-device and target-free overlay measurement based on CD-SEM contours has been assessed on SRAM patterns and showed promising results. The work presented here pushes forward this assessment using SEM synthetic images generated from the open-source Nebula simulator of electron-matter interaction. From a layout, a 3D geometry of the measured pattern can be generated, with materials and interfaces carefully defined. Then, a GPU-accelerated Monte-Carlo model simulates in tens of seconds the SEM image. This fast generation of images enables the use of synthetic SEM images in a digital twin system : they can be used to characterize and to challenge the overlay metrology, before applying it to real products. Indeed, a known overlay can be programmed in these images. This way the performances of the measurement algorithm can be assessed with a ground truth reference. Firstly, imaging parameters such as pixel size and noise have been varied in a wide range. This demonstrated a good accuracy and precision inside a defined measurement window with a coefficient of correlation above 0.996 and an offset lower than 0.2nm. In a second part, the influence of the pattern measured has been investigated and experimental results on SRAM could be reproduced using synthetic images. The origin of the loss of sensitivity has been identified and improvements in the contour extractions and used template led to a correlation with a slope of 1.03, an offset of 0.1nm and a Root Mean Square Deviation of 1.36 nm. Finally, the developed digital twin already showed behaviors in the measurement that were hidden in the on-wafer experiments, that helped assessing the method and which will be used in the future to define guidelines for template based SEM-OVL measurements.