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A Σ∆ phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The Σ∆ enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroelectronics technology. The power consumption is about 29 mW without buffers under 1.2 V for a 500-MHz operating frequency.

This paper presents theoretical results on phase modulation of injection locked oscillators. Experimental results on a 2-GHz fifth SuBharmonic Injection Locked Oscillator (SBILO) integrated in a 0.35-µm BiCMOS STMicroelectronics technology are presented. Measured phase error added by the SBILO once locked by a GMSK modulated signal is negligible.

This paper describes a 5GHz Analog Phase Interpolator (API) for clock synthesis and clock data recovery dedicated to multi-gigabit/s serial link applications. The system includes a 10GHz LC Phase Locked Loop for clock generation and an Analog Phase Interpolator implemented with Current Mode Logic (CML) offering better phase noise and speed performances compared to CMOS logic. It has been implemented in ST's 65nm RfCMOS technology. The core of the API occupies a silicon area of 0.09x 0.17mm2 and dissipates less than 22.56mW from a 1.2V voltage supply.

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