An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic range (SFDR) is 62 dB. The total power dissipation is 25.4 mW from 3.0 V. The active analog area is 0.11 mm 2. Index Terms-Adaptive systems, analog-digital conversion, calibration, CMOS analog integrated circuits.

Given that a greater degree of motion was seen with PLL resection combined with ventral foraminotomy, we recommend that PLL resection be performed when performing CDA. In our benchtop model, unilateral and bilateral posterior foraminotomies were not associated with the creation of significant sagittal rotational or AP translational instability.

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