The study aimed at the investigation and application of SnS thin film semiconductor as a channel layer semiconductor in the assembly of an electric double layer field effect transistor which is important for the achievement and development of novel device concepts, applications and tuning of physical properties of materials since the reported EDLFET and the modulation of electronic states have so far been realised on oxides, nitrides, carbon nanotubes and organic semiconductor but has been rarely reported for the chalcogenides. Honey was used as a gel like electrolytic gate dielectric to generate an enhanced electric field response over SnS semiconductor channel layer and due to its ability to produces high on-current and low voltage operation while forming an ionic gel-like solution similar to ionic gels which consist of ionic liguids. SnS gated honey Electric double layer field effect transistor was assembled using tin sulphide (SnS) thin film as semiconductor channel layer and honey as gate dielectric. The measured gate capacitance of honey using LCR meter was measured as 2.15 μF/ cm2 while the dielectric constant is 20.50. The semiconductor layer was deposited using Aerosol assisted chemical vapour deposition and annealed in open air at 250 on an etched region about the middle of a 4×4 mm FTO glass substrate with the source and drain electrode region defined by the etching and masking at the two ends of the substrate. Iridium was used as the gate electrode while a copper wire was masked to the source and drain region to create electrode contact. The Profilometry, X-ray diffraction, Scanning electron microscope, Energy dispersive X-ray spectroscopy, Hall Effect measurement and digital multimeters were used to characterise the device. The SnS thin film was found to be polycrystalline consisting of Sn and S elements with define grains, an optical band of 1.42 eV and of 0.4 μm thickness. The transistor operated with a p type channel conductivity in a depletion mode with a field effect mobility of 16.67 cm2/Vs, cut-off voltage of 1.6 V, Drain saturation current of1.35μA, a transconductance of -809.61 nA/V and a sub threshold slope of -1.6 Vdec-1 which is comparable to standard specifications in Electronics Data sheets. Positive gate bias results in a shift in the cut off voltage due to charge trapping in the channel/dielectric interface.

Sourcing for an alternative to the liquid electrolyte in dye-sensitized solar cells (DSSCs) have been the subject of interest in the photovoltaic horizon. Herein, we reported by means of simulation, the performance of dye-sensitized solar cell by replacing the liquid electrolyte with a copper (I) thiocyanate (CuSCN) hole conductor. The study was carried out using Solar Capacitance Simulation Software (SCAPS) which is based on poisson and continuity equations. The simulation was done based on an n-i-p proposed architecture of FTO/TiO2/N719/CuSCN/Pt. The result of the initial device gave a Power Conversion Efficiency (PCE), Fill Factor (FF), Short Circuit Current Density (Jsc) and Open Circuit Voltage (Voc) of 5.71 %, 78.32 %, 6.23 mAcm-2, and 1.17 V. After optimizing input parameters to obtain 1×109 cm-2 for CuSCN/N719 interface defect density, 280 K for temperature, 1.0 μm for N719 dye thickness, 0.4 μm for TiO2 thickness, Pt for metal back contact, and 0.2 μm for CuSCN thickness, the overall device performance of 7.379 % for PCE, 77.983 % for FF, 7.185 mAcm-2 for Jsc and 1.317 V for Voc were obtained. When compared with the initial device, the optimized results showed an enhanced performance of ~ 1.29 times, 1.15 times, and 1.13 times in PCE, Jsc, and Voc over the initial device. The results obtained are encouraging and the findings will serve as a baseline to researchers involved in the fabrication of novel high-performance solid-state DSSCs to realize its appealing nature for industry scalability.

The study aimed at enhancement and optimisation of SnS conductivity via annealing for field effect transistor’s semiconductor channel layer application. Interstitials and vacancies in SnS films are known to cause carrier traps which limit charge carriers and hence limit the achievement of the threshold voltage for a field effect transistor operation. Tuning of SnS conductivity for transistor application is of emerging interest for novel device operation. SnS thin film semiconductors of 0.4 thickness were deposited using Aerosol assisted chemical vapour deposition and annealed in open air at annealing temperatures of150, 200, 250, 300 and 350 . Variation of the annealing temperature from 150 through 250 enhances the crystallinity of the annealed thin film samples by increasing the number of crystallites of the annealed films which is also buttress by the decreasing values of FWHM. However a further decrease in crystallite size at higher annealing temperature of 300 to 350 was observed which could be attributed to the fragmentation of clusters of crystallites at higher annealing temperature. Increase in annealing temperature increases grain size leading to the reduction in grain boundaries and potential barrier thereby changing the structure and phase of the films which in essence affects the electrical conductivity of the SnS thin films. The films annealed at 250 exhibited optimum conductivity. The average hall coefficients of the samples deposited at 150 to 250 were positive which indicates that the films annealed at this temperature range are of p type conduction while the average hall coefficients of the samples deposited at 300 and 350 were negative indicating that the films are of n type conduction. The conductivity change is essential for the use of SnS as a semiconductor channel layer especially in a field effect transistor where the device can be tuned to work as a p type or n type semiconductor channel layer.

This study is focused on the investigation of SnS thin film for transistor application. Electron trap which is associated with grain boundary effect affects the electrical conductivity of SnS semiconductor thin film thereby militating the attainment of the threshold voltage required for transistor operation. Grain size and grain boundary is a function of a semiconductor’s thickness. SnS semiconductor thin films of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition on glass substrates. Profilometry, Scanning electron microscope, Energy dispersive X-ray spectroscopy and hall measurement were used to characterise the composition, microstructure and electrical properties of the SnS thin film.  SnS thin films were found to consist of Sn and S elements whose composition varied with increase in thickness. The film conductivity was found to vary with grain size and grain boundary which is a function of the film thickness. The SnS film of 0.4 μm thickness shows optimal grain growth with a grain size of 130.31 nm signifying an optimum for the as deposited SnS films as the larger grains reduces the number of grain boundaries and charge trap density which allows charge carriers to move freely in the lattice thereby causing a reduction in resistivity and increase in conductivity of the films which is essential in obtaining the threshold voltage for a transistor semiconductor channel layer operation. The carrier concentration of due to low resistivity of 3.612 ×105 Ωcm of 0.4 μm SnS thin film thickness is optimum and favours the attainment of the threshold voltage for a field effect transistor operation hence the application of SnS thin film as a semiconductor channel layer in a field effect transistor.

SnS semiconductor thin film of 0.20, 0.25, 0.30, 0.35, 0.40 μm were deposited using aerosol assisted chemical vapour deposition (AACV) on glass substrates and were investigated for use in a field effect transistor. Profilometry, X-ray diffraction, Scanning electron microscope and Energy dispersive X-ray spectroscopy were used to characterise the structural and microstructural properties of the SnS semiconductor. The SnS thin film was found to initially consist of a single crystal at thickness of 0.20 to 0.25μm after which it becomes polycrystalline with an orthorhombic crystal structure consisting of Sn and S elements whose composition varied with increase in thickness. The SnS film of 0.4 μm thickness shows a more uniform grain distribution and growth with a crystal size of 60.57 nm and grain size of 130.31 nm signifying an optimum for the as deposited SnS films as the larger grains reduces the number of grain boundaries and charge trap density hence allowing charge carriers to move freely in the lattice thereby causing a reduction in resistivity, increase in conductivity of the films and enhanced energy band gap which are essentially parameters for a semiconductor material for application in a field effect transistor.