Memory is a storage space that is essential for storing the repetitive data and the instructions to perform an operation. In modern processors speed has been increased significantly but memory enhancements are mainly focusing on the ability to store more data in less space and to reduce the latency. Content Addressable Memory (CAM) cells are preferred over SRAM cells as they are faster and gives the address of the matched data whereas SRAM uses address to access particular data. The circuit of Modified Pre-charge free CAM cell proposed in this paper is made up of basic 6T SRAM cell (2 cross-coupled inverters and 2 access transistors) and separate comparison circuit (1 PMOS and 1 NMOS transistor). The 8X8 memory array consists of memory cells, row and column decoders, encoder, pre-charge circuits, sense amplifiers and write driver circuits. The various parameters like delay, dynamic power and power delay product are measured and compared with other CAM cells. CADENCE Virtuoso Tool is used for designing the various circuits in 90 nm technology. The simulation results demonstrate that the suggested CAM cell outperforms other cells, hence it is employed to create the array structure. The 8X8 CAM array based on MPF CAM cell has less power and less delay when compared with other array structures.

Cache memory is a storage space that is essential for storing the repetitive data and the instructions to perform an operation. In modern processors speed has been increased significantly but memory enhancements are mainly focusing on the ability to store more data in less space and to reduce the latency. The circuit of 10 T SRAM cell based on PNN Inverter proposed in this paper is made up of 2 cross-coupled PNN inverters (1 PMOS and 2 NMOS transistors), single ended separate read circuit (2 NMOS transistors) and 2 access transistors (2 NMOS). Different leakage current control techniques like LECTOR and KLECTOR are applied to the 10T PPN and 10T PNN SRAM cells to improve their hold performance and their results are compared. The 8X8 memory array consists of memory cells, row and column decoders, pre-charge circuits, sense amplifiers and write driver circuits. The various parameters like delay, dynamic power, power delay product, leakage power and static noise margin for read, write, and hold operations are measured and compared with other SRAM cells. CADENCE Virtuoso Tool is used for designing the various circuits in 90 nm technology. Simulation results shows that the proposed SRAM cell has better performance comparing to other cells so it is used for creating the array structure. The 8X8 10T PNN SRAM cell-based array has less power and less delay when compared with other array structures.