Sparse general matrix multiplication (SpGEMM) is a fundamental building block for many realworld applications. Since SpGEMM is a well-known memory-bounded application with vast and irregular memory accesses, considering the memory access efficiency is of critical importance for optimizing SpGEMM. Yet, the existing methods put less consideration into the memory subsystem and achieved suboptimal performance. In this paper, we thoroughly analyze the memory access patterns of SpGEMM and their influences on the memory subsystem. Based on the analysis, we propose a novel and more efficient accumulation method named BRMerge for the multi-core CPU architectures. The BRMerge accumulation method follows the row-wise dataflow. It first accesses the B matrix, generates the intermediate lists for one output row, and stores these intermediate lists in a consecutive memory space, which is implemented by a ping-pong buffer. It then immediately merges these intermediate lists generated in the previous phase two by two in a tree-like hierarchy between two ping-pong buffers. The architectural benefits of BRMerge are 1) streaming access patterns, 2) minimized TLB cache misses, and 3) reasonably high L1/L2 cache hit rates, which result in both low access latency and high bandwidth utilization when performing SpGEMM. Based on the BRMerge accumulation method, we propose two SpGEMM libraries named BRMerge-Upper and BRMerge-Precise, which use different allocation methods. Performance evaluations with 26 commonly used benchmarks on two CPU servers show that the proposed SpGEMM libraries significantly outperform the state-of-the-art SpGEMM libraries.

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Wireless Body Area Network (WBAN) has been widely applied to biomedical applications today, in which errorcorrecting code (ECC) is utilized to improve reliability. In WBAN, ECC overhead can be comparable to transmit power because of the extremely short transmission distance. Therefore, as the most power-hungry component, ECC decoder should be carefully designed. In this letter, we first present an exploration for energy efficient ECC decoder in various practical scenarios of WBAN. A framework is proposed for the exploration based on an energy efficiency model of WBAN, in which all significant parameters within the design space are considered. Taking advantage of the model, we evaluate the energy efficiency of WBAN nodes when type-II Chase soft-decision decoder or hard-decision decoder is utilized. The exploration determines energy-efficient decoder for each scenario and shows that energy-efficient decoder can achieve as much as 80% higher energy efficiency than the alternative.