The current-mode ADC chip-prototype for the readout of DEPFET particle pixel-detectors with high spatial resolution is presented. The planned application of these DEPFET detectors are vertex detectors for ILC and Belle II. The chip has 72 ADC channels. Every channel processes the input signals using two cyclic ADCs that operate in parallel. The cyclic ADCs are based on current-mode memory cells. The measured signal to noise ratio of one ADC is about 660 (fast ADC variant: 520) and its conversion time is 320 ns (fast ADC variant: 160 ns) in the case of 8-bit resolution. Redundant signed-digit cyclic conversion is used for automated digital error correction. One ADC-core occupies only 40 m 55 m, its static power consumption is 0.96 mW. Besides the two ADCs, every channel contains a regulated cascode and two additional current-mode memory cells that allow double-sampling of the input signal. Due to the need for high radiation tolerance, the chip has been implemented in a 180 nm CMOS technology using enclosed NMOS gate layouts. Novel radiation-hard circuits have been used. The chip has also been used to read out a small DEPFET test matrix.

For the readout of the TRD sub-detector of the planned fixed-target CBM experiment at FAIR/GSI (Darmstadt, Germany), a new self-triggered amplification and digitization mixed-signal chip is being developed. The final asic will have 32-64 channels each composed of a low noise and power charge preamplifier, a 7-9 Bit pipeline ADC running at about 25 MSamples/s and some digital data processing units carrying out detector specific tasks such as ion-tail cancellation and baseline correction. A token ring network will act as a balancing arbiter between the channels and the output serializer. The latest 180 nm test-chip has 26 preamplifier/shaper channels and 8 ADCs. For control signal generation and output decoding two synthesized blocks have also been integrated. By connecting both preamplifier and ADC, digital snap-shots of injected test-pulses have been recorded successfully, showing the proper oscilloscope-like operation of the whole mixed-signal data chain from analog amplification to digital output encoding.

For the charge readout of the TRD sub-detector of the upcoming fixed-target experiment CBM at FAIR/GSI, a dedicated 32-channel mixed-signal readout ASIC is being devel oped in 180 nm. The first full-blown version called SPADIC 1.0 was submitted end of 2011 and is currently being tested in the laboratory. The SPADIC ASIC is a complete readout system from analog input charge to digital output protocol and hereby provides an oscilloscope-like readout scheme. Each channel consists of an amplifier (CSA, 800e-ENC), a continuously running pipeline ADC (8 bit effective, 25 MSamples/s), a digital filter (4-stage IIR), a hit detection logic (self-triggered), a message building mechanism, and finally an output buffer. The messages in the output buffers are arbitrated to one message stream, which subsequently is transmit ted via a complex protocol serially over two 500 Mbitfs LVDS links out of the chip. The list of additional features is long, making the SPADIC ASIC a flexible solution for various detector applications.