The purpose of this investigation was to assess the effects of a cooperative learning strategy in physical education on academic learning time, the percentage of correct trials, the total number of trials, and correct trials. A cooperative learning strategy, Performer and Coach Earn Rewards (PACER), was implemented in a sixth-grade physical education class. Four children (two boys and two girls) participated. An ABAB withdrawal design was used to assess the effects of PACER during an 18-day unit of instruction. Functional relationships were demonstrated for the percentage of correct trials for all participants. Interestingly, low-skilled students performed as well as their average- and highly skilled counterparts.

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

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