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State minimization of incompletely specified machines is an important step of FSM synthesis. An exact algorithm consists of generation of prime compatibles and solution of a binate covering problem. This paper presents an implicit algorithm for exact state minimization of FSM's. We describe how to do implicit prime computation and implicit binate covering. We show that we can handle sets of compatibles and prime compatibles of cardinality up to 2 1500 . We present the first published algorithm for fully implicit exact binate covering. We show that we can reduce and solve binate tables with up to 10 6 rows and columns. The entire branch-and-bound procedure is carried on implicitly. We indicate also where such examples arise in practice.

We survey techniques for solving binate covering problems, an optimization step often occurring in logic synthesis applications. Standard exact solutions are found with a branchand-bound exhaustive search, made more efficient by bounding away regions of the search space. Standard approaches are said to be explicit because they work on a direct representation of the binate table, usually as a matrix. Recently, covering problems involving large tables have been attacked with implicit techniques. They are based on the representation by reducedordered binary decision diagrams of an encoding of the binate table. We show how table reductions, computation of a lower bound, and of a branching column can be performed on the table so represented. We report experiments for two different applications that demonstrate that implicit techniques handle instances beyond the reach of explicit techniques. Various aspects of our original research are presented for the first time, together with a selection of the most important old and new results scattered in many sources. Tiziano Villa, for a photograph and biography, see this issue, p. 675. Timothy Kam (M'87), for a photograph and biography, see this issue, p. 675.

Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we present a new mapper aimed at mitigating structural bias. It is based on a simplified cut-based boolean matching algorithm, and using the speed afforded by this simplification we explore two ideas to reduce structural bias. The first, called lossless synthesis, leverages recent advances in structure-based combinational equivalence checking to combine the different networks seen during technology independent synthesis into a single network with choices in a scalable manner. We show how cut-based mapping extends naturally to handle such networks with choices. The second idea is to combine several library gates into a single gate (called a supergate) in order to make the matching process less local. We show how supergates help address the structural bias problem, and how they fit naturally into the cut-based boolean matching scheme. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area and run-time on academic and industrial benchmarks.

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