In this study, we investigate the composite La 2 O 3 /HfO 2 high k dielectric as the gate oxide for n-InAs metal-oxide semiconductor (MOS) capacitor. The La 2 O 3 was used for its high k value and HfO 2 was used as the diffusion barrier and was deposited between La 2 O 3 and InGaAs to prevent the Inter-diffusion between InAs and La 2 O 3 layers after post deposition annealing (PDA). Finally, we demonstrate the La 2 O 3 /HfO 2 composite oxide structure as the high K dielectric for n-InAs MOS capacitor with enhanced capacitance for the MOS capacitor. IntroductionThe IC performance improves rapidly in the past decade due to the continuous scaling of metal-oxide-semiconductor field effect transistors (MOSFET). However, as channel lengths are scaled to the 22nm node, conventional Si-based technology comes to the scaling limit. III-V MOSFET is regarded as one of the promising candidates for next generation devices, due to the high electron mobility of III-V materials compared to that of Si. The integration of high mobility -compound semiconductors with high-k dielectrics is very important for further scale down the MOSFET devices for high speed logic applications. Previous study has focused on deposited SiO 2 gate oxides [1]. However, SiO 2 would induce serious gate leakage and high bulk charge densities. Recently, several high-k materials had been studied as gate dielectrics for III-V devices, such as Al 2 O 3 , HfO 2 , and Gd 2 O 3 et al [2][3].The In 0.7 Ga 0.3 As MOS devices with Al 2 O 3 and HfO 2 as gate dielectrics have been demonstrated [4][5]. Among III-V materials, InAs has the highest electron mobility and also the InAs based device has the lowest turn on voltage. On the other hand, InAs which does not contain Ga atoms will avoid Gallium oxide formation which can't be avoided for In X Ga 1-X As layer, the Gallium oxide usually has high surface trap density and is difficult to remove by surface treatment [6]. Therefore, InAs is an excellent candidate as channel material for next generation low power, high-speed III-V CMOS logic applications. Furthermore, HfO 2 and La 2 O 3 are known to have dielectric constant 4-5 times higher than SiO 2 [7]. In this study, n-InAs MOS capacitors with HfO 2 and La 2 O 3 dielectric films are fabricated and the electrical characteristics of the MOS capacitors are evaluated. ExperimentsThe MOS capacitor structure includes: a 10nm n-In 0.53 Ga 0.47 As layer, a 3nm nIn 0.7 Ga 0.3 As layer and a 5nm n-InAs layer with Si doping concentration of 5х10 17 (cm -3 ), the structure was grown on a n-InP substrate. For the device process, first, 5nm HfO 2 dielectric layer and 10nm La 2 O 3 dielectric layer were deposited sequentially by MBE method on the epi-taxy InP wafer and followed by 500 RTA annealing. Then, the W electrode was deposited on the top of the dielectric and Au Ohmic was deposited on the back of the substrate to form the MOS capacitor.

This study investigates electrical characteristics and the formation mechanism of the Cu/Ge/Pd Ohmic contact to n-type InGaAs. After annealing the contact at 250°C for 20 min, Cu 3 Ge and Pd 12 Ga 5 As 2 compounds formed and Ge diffused into the InGaAs layer, achieving a heavily doped InGaAs layer with a low contact resistivity of 1 9 10 À6 X cm 2 . Thermal stability tests were performed on the Cu/Ge/Pd Ohmic contact to InGaAs after Ohmic contact formation, showing no obvious degradation after a 72 h reliability test at 250°C. The results indicate excellent electrical characteristics and thermal stability using Cu/Ge/Pd as an Ohmic contact metal to an n-InGaAs layer.

Post deposition annealing is a critical process for the quality improvement of gate oxides on Ⅲ-Ⅴ MOS capacitors. Though high temperature annealing would effectively repair defects, it could also induce undesired electrical characteristics due to the crystallization of the gate oxide. In this work, we investigate the novel two steps annealing technique to improve the HfO 2 /In 0.7 Ga 0.3 As MOSCAP properties. The two steps process takes advantage of 1 st high temperature annealing (550 0 C) to improve the interface quality and 2 nd low temperature annealing (450 0 C) for curing bulk oxide without oxide crystallization. The two steps annealing technique greatly improves the HfO 2 /In 0.7 Ga 0.3 As properties as compared to single step process and is expected to be helpful for future Ⅲ-Ⅴ MOSFET development. IntroductionThe IC performance improves rapidly in the past decade due to the continuous scaling of metal-oxide-semiconductor field effect transistors (MOSFET). However, as channel lengths are down to the 22nm node, conventional Si-based technology comes to the serious scaling limits. The high mobility Ⅲ-Ⅴ channel materials have attracted much attention. Among the choices of several alternative channels, In-rich InGaAs exhibits superior characteristics of high electron mobility, high saturation drift velocity, and high transconductance when used as n-channel materials (1).The lack of native oxides for Ⅲ-Ⅴ channel materials is a limitation for Ⅲ-Ⅴ MOSFET development.

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