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This paper reports on a novel and highly innovative technology to interconnect back‐contact cells. First, a background section explains the currently developed interconnection technologies. Then, our novel concept is introduced: interconnection of the cells is achieved with a woven fabric, combining both conductive wires, needed for the interconnection, and insulating wires, crucial to avoid shunting between both polarities at the backside of the cell. Weaving also allows out‐of‐plane stress relief features. In the third section, we explain that our technology combines the advantages of multi‐wire interconnection such as low‐stress and reduced resistive losses with known and low‐cost materials of traditional module assembly. Additional to previous publications, we demonstrate that the technology can be tuned broadly in terms of costs and resistive losses using an optimized interconnection pattern. These resistive loss simulations are also validated with the measured additional resistance in IBC test samples. We also present a preliminary thermal cycling test with promising results. Finally, first functional demonstrators IBC cells are fabricated, disclosing the process flow and initial technology developments. These results clearly demonstrate the proof‐of‐concept of the woven interconnection fabric, and based on electrical characterization we provide suggestions for improvements. Copyright © 2016 John Wiley & Sons, Ltd.

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 µm EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated.

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