System-in-Package (SiP) is generally regarded as the long-awaited renaissance of multichip module (MCM) since its firstly introduced and assembled in a decade ago. As a matter of fact, simultaneously satisfaction of a number of key determining factors as well as the timely emergences of certain critical technologies are the reasons for the expeditious development of SiP in recent years, including the advancements in assembly technology, novel development of low-cost, high performance substrate materials, and more importantly, massive demands on high-performance and compact product profiles. Recent report has outlined the major reasons for industry to adopt SiP in their products, comprising miniaturization (37%), electromagnetic insulation (EMI) noise reduction (26%), lower power consumption (13%), total cost reduction (12%) and circuitry simplification in high speed applications (12%).Nevertheless, there are still certain key issues necessary to be overcome for the robust development of SiP technology, for example, the availability of bare die and known good die (KGD), overall assembly yield, overall signal integrity of the system module particularly in high-speed/high frequency applications, heat dissipation in densely packed modules, lifetime prediction, etc. The outsourcing customs of the industry to date have also presented considerable challenges to the prevalence of SiP. Moreover, intimate collaborations among various sectors along the materials supply chain, semiconductor and assembly and testing (SAT) subcontractors are definitely the turnkey solution to timely deliver prototype products prior to mass production. Providing robust substrate design to insure first-pass success with the right design technologies is also challenging in order to satisfy the demands on low-cost, optimal performance and outstanding reliability.In this study we first try to elucidate the factors determining the successfulness of SiP, from the perspective of volume-in-production, technology advancement favoring SiP development and demands from various applications. Afterwards, we illustrate the challenges that the industries along the entire electronic packaging supply chain are facing in SiP implementation. We put forward to address the critical demands on having a design centre with integrated capabilities and experiences on packaging design, substrate layout, EM and thermal-mechanical analyses, package characterizations & prototyping and coordinations among various companies in order to assist the customers in developing advanced IC/module packaging solutions for mass production of their new products in a timely manner.

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Package-on-Package (PoP) is one of the major 3D packaging approaches. It vertically combines discrete memory and logic Ball Grid Array (BGA) packages, where one package rests on the top of the other. Recently, PoP technologies have attracted more interests, especially for portable electronics related products and applications.ASTRI has developed a new PoP structure, which employs a new bottom package which is over molded Finepitch Ball Gird Array (FBGA) format with mechanically balanced package structure. For the top package, it is a commercial FBGA format with two die stacked inside. Since the new bottom package structure is based on an existing FBGA format, the mold chase is independent of the mold cap and size of the bottom PoP package. The final mold layer for bottom package has a thickness of 0.50mm. The top interface of the bottom PoP package has 136 pads with 0.65mm pitch and a two-row peripheral format, while the bottom interface has 272 pads with 0.65mm pitch and a four-row peripheral format. The size of both top and bottom packages is 14 x 14mm 2 . The 3D finite element (FE) simulator Ansoft HFSS was used to evaluate the high-frequency performance of the new PoP structure. The low-loss and low cross-coupling results indicate that the above PoP offers a promising solution for communication-related products. Physical configuration of the package was evaluated by cross section & scanning electron microscopy (SEM) examination, which showed a favorable interconnection structure. The warpage of the bottom PoP package after assembly process was characterized by a shadow moiré system. The warpage was well controlled by adopting a fully molded structure. The average package warpage value was around 30μm that was well below the warpage target of 80μm widely used in the industry. In this work, the moisture sensitivity level-3 (MSL-3) test was applied to evaluate the reliability of the above package. Board-level reliability including temperature cycling (TC) & drop tests were also evaluated. The results of the reliability tests showed good performance and demonstrated that the above PoP is a viable design. In summary, the above PoP design exhibited promising RF performance, excellent warpage performance, qualified package-level and boardlevel reliability. It offers an effective solution for high-density packages used in the portable consumer electronics.

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