While attention in the realm of computer design has shifted away from the classic DRAM soft-error rate (SER) and focused instead on SRAM and microprocessor latch sensitivities as sources of potential errors, DRAM SER nonetheless remains a challenging problem. This is true even though both cosmic ray-induced and alpha-particle-induced DRAM soft errors have been well modeled and, to a certain degree, well understood. However, the oftenoverlooked alignment of a DRAM hard error and a random soft error can have major reliability, availability, and serviceability (RAS) implications for systems that require an extremely long mean time between failures. The net of this effect is that what appears to be a well-behaved, single-bit soft error ends up overwhelming a seemingly state-of-the-art mitigation technique. This paper describes some of the history of DRAM soft-error discovery and the subsequent development of mitigation strategies. It then examines some architectural considerations that can exacerbate the effect of DRAM soft errors and may have systemlevel implications for today's standard fault-tolerance schemes.

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The typlcal personal computer of today Is used more and more to perform functions and run application programs that are critical to a business's success. One of the biggest probkms that inhibits productivity In this environment is the effect of a lock-up, crash or parity error caused by cosmic-ray radiation-induced soft errors in the DRAM chips. IBM has announced a family of plug-compatible, retrofittable SlMMs wiith built-in ECC to provide a solution to this problem. This paper addresses the challeniges associated with the full functional test of a SlMM with on-board ECG using a very test#-unfriendly industry-standard memory module interface.

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