Digital systems models complexity requires often representation of their structure in graphical form. Also the simulation results of the models are often very extensive and for their effective browsing the proper representation is needed. We have proposed the methods for visualization of the digital systems models structure as well as their simulation outputs. The methods were designed to support the three most popular hardware description languages (HDLs) -VHDL, Verilog, and SystemC. For each language the algorithms were developed for transformation of model structure and simulation results into the common output forms that can be stored in common file formats for all the languages. To verify the solution all the methods were integrated into one system allowing to browse connections between modules on each level of model hierarchy. The simulation results can be displayed in the traditional waveform style, however the values of ports and signals at a particular time can be displayed directly in the visualized structure as well.