To parallelize simulations, independent events have to be identified, which can be executed concurrently. The highest level of parallelism is achieved if the number of events identified as independent is maximized. Traditionally, this identification is based on time and location of events, only allowing parallelization if events on the same simulation entity are executed in timestamp order. To increase the level of parallelism, we propose a novel approach investigating another criterion for independence: If two events on the same simulation entity do not access the same data items in a conflicting manner, they can as well be executed in parallel. To this end, we propose static analysis of the model code for data access. To ease this process we develop the simulation language PSimLa similar to C++ but modified where necessary to increase analyzability without removing essential C++ features. First evaluation results show the potential of this approach and increase the confidence that data-dependency analysis can improve future parallel simulation.

Simulation of wireless systems is highly complex and can only be efficient if the simulation is executed in parallel. To this end, independent events have to be identified to enable their simultaneous execution. Hence, the number of events identified as independent needs to be maximized in order to increase the level of parallelism. Traditionally, dependencies are determined only by time and location of events: If two events take place on the same simulation entity, they must be simulated in timestamp order. Our approach to overcome this limitation is to also investigate data-dependencies between events. This enables event reordering and parallelization even for events at the same simulation entity. To this end, we design the simulation language PSimLa, which aids this process. In this paper, we discuss the PSimLa design and compiler as well as our data-dependency analysis approach in detail and present case studies of wireless network models, speeded up by a factor of 10 on 12 cores where time-based parallelization only achieves a 1.6x speedup.