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Embedded DRAMs (eDRAMs) have superior features for mobile applications, notably low operation power and high bandwidth, compared with high-speed DRAMs such as DDR-SDRAM and XDR-DRAM. However, their standby power is not as attractive as their operation power because of the leakage of high-performance logic transistors and the fact that retention time of their memory cell is not as good as that of commodity DRAMs. For the purpose of reducing the standby power, lowering of BL swing in the refresh period has been reported [1]. However, this approach needs more frequent refresh operation due to a decrease in cellcharge. As a result, overall standby power is scarcely improved.To solve these problems, the extended data retention (EDR) sleep mode is introduced to a 65nm 32Mb eDRAM macro. The retention time is 8-times longer by ECC with no performance degradation.By using ECC with the conventional redundancy, the tolerable number of random failure bits in the memory arrays is increased drastically. The inset in Fig. 8.5.1 shows the yield as a function of the average number of random single failure bits. Horizontal axis shows the ratio of the number of failure bits to the total number of memory cells in the 32Mb macro. Using the conventional redundancy, 0.00015% of average failure bits is tolerable without sacrificing yield. By using ECC, tolerable number of average failure bits increases to 0.015%. This enhancement of tolerance is very effective for extending the retention time of the worst cell after error correction. Figure 8.5.1 shows the typical retentiontime distribution of the 65nm eDRAM. The retention time of the worst bit cell is extended by ECC to a length that is 8-times greater than in the case of only using the redundancy. Figure 8.5.2 shows the concept of the EDR sleep mode. The timing diagrams of conventional macros are also shown for comparison. The refresh intervals with and without ECC, denoted by tREF and tREFECC, are shown in Fig 8.5.2 (a) and (b), respectively. In Fig. 8.5.2 (b), ECC is used in every read/write cycle and tREFECC is 8-times longer than tREF. However, the read/write speed deteriorates due to the check-bit generation and the error correction. To avoid these performance degradations, the EDR sleep mode shown in Fig. 8.5.2 (c) is proposed. The check bits are generated for all the cells at the beginning of the EDR sleep mode, and retention error bits failed in the sleep mode are corrected at the end of the EDR sleep mode. Since ECC operates only at the beginning and end of the sleep mode, the performance of read/write operation is not degraded. During the EDR sleep mode, the MT-CMOS technique with the leakage cut-off transistor is used to suppress the leakage current in the peripheral circuits because the period of refresh cycles is less than 0.1% of the tREFECC.The block diagram of the 32Mb eDRAM macro is shown in Fig. 8.5.3 (a). The macro is divided into eight 4Mb sub-macros. Two groups of 136b global data lines are routed over the memory cell arrays. The 1b error within each 136b data-li...

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Embedded DRAMs have superior features for applications that require very high memory bandwidth, such as graphics and multimedia. To achieve high memory bandwidth, various techniques such as widening input/output pins [1], shrinking the unit array size [2], and performing a read operation and a write operation concurrently [3,4] have been reported. However, these embedded DRAM macros incur considerable area penalty to obtain high memory bandwidth. Figure 14.4.1 shows the cell efficiency versus the memory bandwidth of the macros reported recently. Among the techniques for achieving high bandwidth, the concurrent read/write operation is a very effective method in performing a read-modify-write function and a double-buffer function for the graphics applications. We describe a pseudo-two-port embedded DRAM macro that performs concurrent read/write operations at high frequency without sacrificing cell efficiency. To accomplish this, we introduce, a read/write cross-point switch circuit (RWCC) and distributed steering redundancy switches (DSRS). A 32Mb macro is characterized via a test-chip fabricated in a 65nm embedded DRAM process. We confirm page-mode operating frequency of 833MHz at 1.2V.In the previous work [3,4], in order to realize the concurrent read/write operation, the data lines connecting sense amplifies and input/output circuits are separated into read path and write path. Since this requires additional switches for each sense amplifier, the area overhead of the sense amplifier region is considerable. This decreases the cell efficiency of the macros.Our pseudo-two-port embedded DRAM macro performs a read operation and a write operation concurrently in two different banks. Figure 14.4.2 shows the block diagram of the DRAM macro. A read/write cross-point switch circuit (RWCC) is placed between two adjacent banks. The RWCC consists of 2 nd sense amplifiers (R), write buffers (W), and data path switches. Local read/write data lines (LRWD) are bidirectional data lines in a bank, and global data lines are separated into read path (GRD) and write path (GWD). The RWCC controls connections between GRD/GWD and LRWD according to the address for bank selection and the read/write commands. In this way, the read data from a bank do not collide with the write data to the other bank on the data path. Therefore, the concurrent read/write operation can be performed in different two banks. Since bidirectional data lines in a bank are used in a similar way to a conventional single-port DRAM, the area penalty for the sense amplifier region is eliminated. The macro area overhead for the concurrent read/write operation is less than 1%. Each of the two input ports has a full set of inputs for the address and the control signals for read, write, active, and precharge. The addresses and the commands are independently asserted for each port. Only simultaneous read and simultaneous write command inputs from the two ports are prohibited. During continuous read operations in a bank, write commands are asserted independently to another b...