Abstract. Current day multicore processors employ multi-level cache hierarchy with one or two levels of private caches and a shared last-level cache (LLC). Efficient cache replacement policies at LLC are essential for reducing the off-chip memory traffic as well as contention for memory bandwidth. Cache replacement techniques for unicore LLCs may not be efficient for multicore LLCs as multicore LLCs can be shared by applications with varying access behavior, running simultaneously. One application may dominate another by flooding of cache requests and evicting the useful data of the other application.This paper proposes a new cache replacement policy for shared LLC called Application-aware Cache Replacement (ACR). ACR policy prevents victimizing low-access rate application by a high-access rate application. It dynamically keeps track of maximum life-time of cache lines in shared LLC for each concurrent application and helps in efficient utilization of the cache space. Experimental evaluation of ACR technique for 2-core and 4-core systems using SPEC CPU 2000 and 2006 benchmark suites shows significant speed-up improvement over the least recently used and thread-aware dynamic re-reference interval prediction techniques.

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Modern multi-core systems allow concurrent execution of different applications on a single chip. Such multicores handle the large bandwidth requirement from the processing cores by employing multiple levels of caches with one or two levels of private caches along with a shared last-level cache (LLC). In shared LLC, when applications with varying access behavior compete with each other for space, conventional single core cache replacement techniques can significantly degrade the system performance. In such scenarios, we need an efficient replacement policy for reducing the off-chip memory traffic as well as contention for the memory bandwidth. This paper proposes a novel Application-aware Cache Replacement (ACR) policy for the shared LLC. ACR policy considers the memory access behavior of the applications during the process of victim selection to prevent victimizing a low access rate application by a high-access rate application. \textcolor{red}{ It dynamically tracks the maximum lifetime of cache lines in shared LLC for each concurrent application and helps in efficient utilization of the cache space. Experimental evaluation of ACR policy for 4-core systems, with 16-way set associative 4MB LLC, using SPEC CPU 2000 and 2006 benchmark suites shows a geometric mean speed-up of 8.7% over the least recently used (LRU) replacement policy. We show that the ACR policy performs better than recently proposed thread-aware dynamic re-reference interval prediction (TA-DRRIP) and protecting distance based (PDP) techniques for various 2-core, 4-core and 8-core workloads.

With the advent of multiple cores on a single chip, it is common for the systems to have multi-level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2-level and 3level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called 'SkipCache', which allows an application to choose a 2-level or 3level cache hierarchy during run-time. SkipCache dynamically tracks the applications at shared last-level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co-scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4-core chip multi-processor with multi-programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.