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This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance ([Formula: see text]). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42[Formula: see text]dB to 70.4[Formula: see text]dB. It has provided 9.24[Formula: see text]kHz gain bandwidth (GBW), consuming 64[Formula: see text]nW of quiescent power from a 0.51[Formula: see text]V single power supply at 15[Formula: see text]pF load. The proposed OTA in unity gain configuration has ensured reduced total harmonic distortion (THD) of [Formula: see text][Formula: see text]dB at 200[Formula: see text]Hz frequency and 1[Formula: see text]V[Formula: see text] signal swing. Its fully differential class AB input and output structures have ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise. The Cadence Virtuoso environment using GPDK 180[Formula: see text]nm standard [Formula: see text]-well CMOS process technology has been used to simulate the proposed circuit.

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Operational Transconductance Amplifier (OTA), is a main building block of analog signal systems. This paper presents a novel low-voltage and low-power rail-to-rail wide linear range OTA, operating in weak inversion region. The bulk and source-degenerated input stage provides, rail-to-rail input and output signal swings, whereas the class AB flipped voltage follower generates the bias current for the input stage. To enhance the current drive capability, a positive feedback has been employed at gates of input transistors. The OTA uses a single 0.5 V supply and dissipates 32 nW power to provide 38 dB gain and 50 kHz gain bandwidth product. The Cadence VIRTUOSO environment using UMC 0.18 m CMOS process technology has been used to simulate the proposed circuit. Simulation results showed that the circuit exhibits less than 52 dB total harmonic distortions, for 100 mV (p-p) signal at 200 Hz frequency in its unity gain configuration.

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