An effective electron mobility improvement that uses strain-proximity-free technique (SPFT) has been demonstrated using strain-gate engineering. The electron mobility of nMOSFETs with SPFT exhibits a 15% increase over that of counterpart techniques. The preamorphous layer (PAL) gate structure on the SPFT showed a further performance boost. The electron mobility exhibits a 52% improvement in nMOSFET using a combination of SPFT and PAL gate structure. Furthermore, the gain in electron mobility in the SPFT in combination with PAL gate structure decreases at high temperatures. Gate dielectric interface states and ionized gate impurities inducing carrier scattering will play important roles when operating devices under hightemperature conditions.

An enhanced stress memorization-technique that utilizes a strain proximity free technique ͑SPFT͒ and a stacked-gate structure has been demonstrated by multiple strain-gate engineering. The electron mobility of n-channel metal-oxide semiconductor field effect transistors ͑nMOSFETs͒ with SPFT exhibit a 16% increase compared to that of counterpart techniques. SPFT avoids the limitation of stressor volume for performance improvement in high-density complementary metal oxide semiconductor circuits. We also found that optimization of stacked, random poly-Si-grain gate structure in combination with SPFT can improve mobility further to 22% more than a single poly-Si gate structure without SPFT.In pursuit of high-speed circuit applications, mobility enhancement by local stressor engineering in high-performance complementary metal oxide semiconductor ͑CMOS͒ transistors has been intensively studied using techniques such as dual-contact etch stop layer ͑DCESL͒ and embedded SiGe in the source/drain ͑S/D͒ area. 1-4 Recently, the stress-memorization technique ͑SMT͒ has been reported to enhance electron mobility on n-channel metal-oxide semiconductor field effect transistors ͑nMOSFETs͒ and widely studied by different methods. 5-7 However, most previous studies have demonstrated the performance boost without considering the scalability of the gate density. As the scaling of design rules such as polypitch shrinks in high-density static random access memory circuits ͑as shown on the top of Fig. 1͒, mobility enhancement is limited by stressor-volume and process-integration issues. Introducing longitudinal tensile stress and vertical compressive stress into the channel region are the well known principles of mobility enhancement on nMOSFETs. 8 However, longitudinal tensile stress is limited as the stressor volume reaches its saturation point, causing performance degradation. 9 Moreover, poor Ni-silicide formation and contact process integration issues are induced by stressor residue in highdensity CMOS circuits.In this work, we proposed a strain proximity free technique ͑SPFT͒ to avoid the limitation of stressor volume for performance improvement in high-density CMOS circuits. Stacked a-Si/poly-Si gate structure has been reported to enhance channel stress and electron mobility. 10 We also demonstrated that the stacked gate structure with optimization of a bottom layer of random poly-Si-grain size and thickness can further improve nMOSFET performance. ExperimentalnMOSFETs were fabricated on 6 in. wafers with resistivity of 15-25 ⍀ cm. After the RCA cleaning process, 2.5 Ϯ 0.1 nm gate oxide was grown in a vertical furnace ͑800°C, O 2 ambient͒. Then, the stacked-gate structure was built using poly-Si with optimization of bottom-layer poly-Si grain size and thickness and deposited in the same ambient. The bottom-layer thickness of the stacked gate is near 70 nm. The final gate thickness was kept the same for all samples at 200 nm. The SPFT, whose process flow is illustrated in Fig. 1, is proposed in order to introduce stress into the cha...

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In the current semiconductor industrial scenario, wafers are rinsed in an overflow rinsing tank while being mounted on several lifters prior to most of its manufacturing processes. However, a major drawback of this overflow rinsing methodology is that some of the processing fluid stagnates due to the generated vortices in the regions between the side and middle lifters which entrap some of the flushed particles that further adhere and deteriorate the surface of the wafers. In this work, the hydrodynamics of the flow field inside the wafer rinsing tank with this original lifter orientation setup was studied and compared through numerical simulation and flow visualization using particle image velocimetry (PIV) method, and a strong agreement was found between them in terms of velocity calculation. A new lifter orientation setup was initiated and it was evidenced by the numerical simulation that with this new setup, the generated vortices which are situated opposite to the lifters tilting direction can be displaced significantly in terms of magnitude and distribution. This work presents a new wafer cleaning concept which shows its great potentials in improvement and implementation to the current in-line wafer batch fabrication process without modifying the original design of the rinsing tank.

The impacts of zero-temperature-coefficient (ZTC) points of various strained devices is presented in this letter. The current and mobility are reduced at high temperature by phonon scattering. The degree of mobility reduction becomes severe on devices with multiple strain-gate engineering. The reduction of mobility becomes severe as a result of impurity scattering, which results from gate implantation impurities. The ZTC point is decreased by multiple strain-gate engineering due to the decreased V th.