Interests in advancing 3D design and integration have stimulated this study of connecting two different silicon dies using an organic interposer. This paper reports some of the challenges encountered by the system and silicon designers during the process of 3D integration. The discussion focuses on ways to improve the efficiency of the design flow, integration and verification of a 3D configuration. By considering the strength and weakness of the silicon and system design environments, the two were used in a complementary manner to achieve the 3D integrated design. 2D Design Environment: System verses SiliconIn the traditional 2D design approach, the system design environment for PCB and package is independent of the silicon design environment. The two design environments are optimized for their corresponding disciplines; for instance, silicon design environment is developed for capturing the finely tuned analog circuit, executing the highly automated ASIC place-and-route and digital design flow, and the integration of both analog and digital design. System design environment is developed for a larger physical domain that includes more than one active component like a SoC or DRAM die. An example is a physically distributed system such as the communication channel between components operating at multi-gigabits per second per link. Therefore, system designers have to consider the details in the substrate that provides high quality 10 and power connections to a silicon die, as well as the PCB that supports signal transmission between the component packages.Design tools are advancing rapidly to address the efficiency [1] and cost [2] of designing 3D configurations. However, majority of the system and silicon designs are still 2D-centric. Time for learning and tool investment are needed in order for the designers to migrate to a 3D environment. The observations presented in this paper are a reflection of the challenges designers face prior to or during the transition. 3D Package by Integration of 2D designPackage-in-package (PiP) is one kind of 3D integration that uses components resulting from 2D designs. An example is shown in Figure 1. Based on the implementation of this assembly, each component is designed independent of each other. The physical interfaces are bond wires and BGA balls for flip chip assembly. The dies, as shown in yellow in Figure 1, are from the silicon design environment. The substrates in green are from the system design environment. This PiP configuration involves a relatively small number of connections using the balls and wires. The verification of connectivity may still be handled by manual methods. This kind of 3D integration does not involve direct communication between the system and silicon design, hence there is no top level verification of the integrated system in the design phase. Fig. 1. 3D package from intergration of 2D design using wirebonding for interconnections.Fig. 2. 3D integration of two dies using micro bumps for dieto-die interconnections.

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A 3.2 Gbps XDR™ memory channel has been optimized to achieve a bit rate of 4.8 Gbps. The 24-bit wide memory interface can deliver an aggregate data bandwidth of 14.4 GB/s to support graphics intensive consumer applications such as high refresh rate 3D digital TV. The optimized high performance channel is also designed to satisfy the low-cost constraint of consumer electronics by using wirebond packaging for the SoC and 4-layer PCB.