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RAKE based receivers are the most challenging receiver due to its hardware implementation complexity. To build a cross-correlating RAKE receiver with on-off keying pose significant design challenges due to multipath components. Also process variations in 90 nm CMOS technology impose significant challenges in the clockless system. In this paper, a simple coherent RAKE receiver using single-bit correlation in continuous time is reported. A working chip with fully integrated digital symbol detection without any clocks, ADC and filters for simple and power efficient CMOS implementation. Optimal design of the delay elements in the tapped delayline and the use of pulse width controller blocks (PWC) along the delayline allows narrow pulses through the system. The optimized delayline combined with the continuous-time high speed counter and the match thresholder constitute a complete continuous-time RAKE receiver in CMOS. Initial chip measurement shows that a data rate of 1.5 Mbit/s with a power consumption of 0.78 mW was possible. I. INTRODUCTIONEven though viable UWB systems are not in widespread use, there are many published papers which show great potential towards short range communications requiring low power and low data-rate [1]. Ultra-wideband impulse radio (IR-UWB) is a promising technology due to its good resolution. According to [2], channel estimation, accurate synchronization and high resolution clocks forms the bottleneck to realize a power efficient UWB radio solutions. UWB signals require RAKE or correlation receivers to take full advantage of the available signal energy over a large bandwidth. Because of complexity constraints, a RAKE receiver processes only a subset of the total number of received multipath components. To mitigate the issues of correlator receivers, different configurations have been proposed [3]. Most implementations sacrifice performance for low complexity operation and lacks a power efficient CMOS implementation aiming towards a cost efficient single chip solution. Even if the receiver complexity is overcome by digital techniques, current solutions require an ADC with high sampling frequency to sample and quantize the received signal [3].Continuous-Time Binary-Value (CTBV) signal processing for IR-UWB systems has been developed [4] which is simply based on inherent CMOS process-dependent gate delays combined with a coarse quantizer or a single-bit ADC. By avoiding clocks, power efficient solutions are feasible in standard CMOS. The performance of the CTBV solution is limited by the gate delay and improves with technology scaling. Although process variations pose significant challenges, high-speed and power-efficient CMOS implementations have

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