This paper presents a systematic technique that relates the instructions at the application-level to the cycle average supply noise. Cost metrics affecting supply noise are maximized and the corresponding activity event is mapped to instructions. We performed experiments on an open-source processor and were able to obtain a higher voltage drop (> 20%) when compared to that of random simulation in a significantly less amount of time (96% reduction).
This paper presents a SNR-aware error detection technique for a low-power wavelet lifting transform architecture in JPEG 2000. Power reduction is done by over-scaling the supply voltage (voltage-over-scaling (VOS)). A low-cost SNR-aware detection logic is integrated into the discrete wavelet lifting transform architecture, to check if the image quality degradation caused by the resulting timing errors is acceptable, in order to determine the optimal voltage setting in operating condition at run time. The technique behind the SNR-aware detection logic is the weighted checksum code. It is shown that image quality measured in SNR can be correlated with the image checksum difference. If the image checksum difference is above a certain threshold, the SNR of the image will be below the minimal requirement and image quality will be unacceptable. This novel quality-based error detection is significantly different from traditional error detection schemes which look for exact data equivalence. The technique is useful in exploring optimal voltage configurations for Dynamic Voltage Scaling (DVS).
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