In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100µm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature instability) measurements. It is found that wafer thinning has negligible impact on Vt of I/O devices. However, we have seen a small impact on the channel leakage, and a moderate impact on saturation currents of high performance core devices. The channel current is reduced ~5% for NMOS, while there is a ~10% enhancement in the PMOS device. Device reliability was assessed using NBTI and no degradation is seen on the devices. This confirms that the thinning did not impact the front end of line gate oxide integrity.

As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness and the final via reveal process. It can compensate for poor via fabrication depth uniformity and less than ideal temporary bonding total thickness variation (TTV). In this paper we will demonstrate the utility of two tools that when used together can systematically produce thin TSV containing wafers to their optimal thickness while protecting the wafers from particulate contamination. The first instrument in this process scheme is a metrology tool that utilizes IR reflectance to measure the silicon thickness remaining between the bottom of the TSV and backside surface of the wafer. These measurements are then transferred to a special grinding tool that can interpret the data and make changes to the grinding depth within the wafer so as to leave thickness of silicon above the TSVs as uniform as possible. Having removed the bulk of the Si through mechanical grinding and Chem/Mech polishing, the next step in the via-middle process is to remove the last few microns of Si overburden to expose the vias. By leaving a shallower Si layer above the TSV during the thinning process compared to current process, the final via reveal process time can be reduced. Also the need for rework in this process because of the wafer-to-wafer variability in the remaining silicon thickness above the TSV can be eliminated. In addition to measuring the pre-grinding Si thickness, the IR reflectance measurement tool can be used to verify the remaining silicon thickness post grind, establishing thinning process feedback and via reveal process feed-forward data.